Elastic Node Middleware
Contact: Christopher Cichiwskyj
Incorporating two completely different types of computing hardware into a single platform however increases the complexity of developing applications for such a device. It requires multiple different skillsets since MCUs are typically programmed using C/C++ while FPGAs use very different hardware description languages (HDLs).
To ease the development for embedded programmers on the Elastic Node this project focuses around developing a minimalistic middleware. It aims to automate certain management tasks like reconfiguring the FPGA, managing its power state or communicating between MCU and FPGA, as well as control the data flow of the embedded application between the MCU and the FPGA.
Additionally the middleware will help to exploit the FPGAs potential especially for embedded applications by using its reconfiguration capabilities to its full extent. Allowing the FPGA to quickly switch between different configurations enables an application to solve even more complex problems by logically connecting different configurations to combine their capabilities. This not only allows for more powerful algorithms to be executable on an embedded device, but also makes it possible for certain algorithms to be run at all. Due to the embedded and low-power nature of the FPGAs used in the Elastic Node, the available resources are rather limited, making it impossible to run a single very complex architecture at once. By reconfiguring in a quick succession an architecture previously to large to fit into the FPGA can now be split into multiple configurations and then executed.
Allowing for collaborative execution of FPGA configurations requires a precise control of the data flow between each FPGA configuration and requires to consider the data dependencies between configurations to be able to schedule the different configurations to be executed in the most efficient way.
This project currently works on the following aspects:
- Data dependency in configuration groups: One of the main goals in this project is to allow an efficient execution of a group of logically connected FPGA configurations. The greatest challenge hereby is the data dependency between these configurations, i.e. which calculation result of a configuration is the input for which subsequent configuration. In here the question remains, how to model this data dependency in such a manner that is suitable for MCUs, as well as what impact this has on the execution order of configurations.
- Data flow management: Another question linked to this is how data is managed and buffered through multiple reconfigurations, in which the FPGA's current state is typically lost. Data needs to be transferred beforehand to an external buffer, however using the MCU's internal RAM will in most application cases not suffice, especially for very complex configuration groups. One possible for this is the usage of an external RAM chip, accessible by both the FPGA and the MCU. For the same reason of the FPGA not storing states through reconfigurations, that external RAM chip needs to be managed by the MCU. This raises the question, what the most efficient way is to store, manage and transfer the data with regards to the configuration group's data dependencies.
- IDLs for easier integration: Each configuration and configuration group contains, what we call a "hardware function", which logically speaking solves exactly one problem. To access such a hardware function from inside a C/C++ application running on the MCU it needs an interface, defining the input and output types, in the case of configuration groups the data dependencies as well. To reduce the development effort of manually writing these interfaces, it being also a possibly very error prone process, we propose a system using Interface Description Languages (IDL) to autogenerate such code. It requires FPGA-developers as experts of their own work, to create such a description of their configuration, that defines its aforementioned aspects. Such a system would also allow for classical embedded programmers, with no prior HDL knowledge to combine preexisting configurations, possibly standalone, into a configuration group, by using their IDL definitions and combine them by simply writing a overarching IDL description.
During the remainder of this project the following aspects will be analysed:
- Efficient execution through minimising reconfiguration: Using reconfiguration in a quick succession allows to create new types of applications for embedded systems. Reconfiguration itself however has a certain time overhead, resulting in longer times that the FPGA has to remain active, thus reducing the overall energy efficiency of the system. When tasks can be scheduled in advance and tasks or task groups can consist of executing a FPGA configuration or set of configurations, respectively, this knowledge can be used to optimise the overall execution order of such tasks. In this scenario tasks that use the same configuration can be scheduled consecutively to reuse the same configuration and thus reducing the number of times that the Elastic Node needs to reconfigure. This however can possible require to reevalaute the data flow management, if task groups containing the same configuration as later tasks can be interrupted in their execution. While this can mean a reduced energy consumption, it increases the data flow management's complexity as data needs to be buffered to a possibly larger extend.