Group Head: Dr. -Ing. Andreas Erbslöh

Hardware Accelerators based on pre-computed 1DCNNs

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Our research focuses on optimizing AI models, particularly deep learning (DL) architectures, for deployment on resource-constrained IoT devices such as embedded FPGAs. The focus is especially on the quantization of neural networks, i.e. the reduction of numerical precision of model parameters to decrease memory usage and computational load, as well as on the use of transformer models.

​​In this context, we generally investigate optimizations for the training of networks while striving for the quickest and most efficient computations possible, for instance, through the use of separable convolutions.

In addition, in quantised neural networks (QNN), a low bit depth of two or fewer bits, in conjunction with the properties of FPGAs, allows operations within the network to be pre-computed to be stored in the LUTs of the configurable logic blocks for the shortest possible access time.

Contact: Lukas Einhaus, M.Sc. | Recent Publication

Hardware Accelerators using Delta Compression

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​​The increasing size of modern neural networks poses significant challenges for embedded systems. Especially in the context of energy-efficient hardware such as FPGAs or microcontrollers, there is a growing need for methods that reduce memory consumption and computational effort without substantially effecting model quality.

One approach explored in our research is delta compression. Instead of storing full model parameters, only deltas are retained. Since Deltas can be compressed with less loss of information, considerable memory savings can be achieved which enables the deployment of larger models in small systems. Delta compression opens up new opportunities for using AI models in embedded environments. It provides an alternative to heavily quantized or structurally reduced network architectures and allows more complex models to operate in resource-constrained settings. At the same time, the compression process almost inevitably introduces information loss, which may impact model performance. Developing suitable methods for error mitigation and adaptive compression strategies is therefore a central topic of ongoing research.

In the long term, delta compression will be combined with additional optimization techniques such as structural pruning or quantization-aware training to enable AI models that are both robust and resource-efficient.

Contact: David Peter Federl, M.Sc. | Recent Publication

End-to-End Signal Processing

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​​The End-to-End Signal Processing research area focuses on the efficient acquisition, processing, and interpretation of neural signals in real time. Its objective is to develop high-performance signal processing pipelines capable of analyzing large volumes of biological data with high temporal and spatial resolution, while extracting meaningful information. Such systems provide the foundation for a wide range of neurotechnology applications, particularly in the fields of invasive Brain–Computer Interfaces (BCIs) and closed-loop systems.

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​To enable efficient implementation on implantable or wearable hardware platforms, the entire data stream and all associated processing methods must be optimized with respect to accuracy, latency, resource utilization, and energy efficiency. This end-to-end approach enables the development of application-specific solutions. Since the underlying algorithms often impose demanding hardware requirements, research also focuses on techniques such as quantization, model compression, highly specialized hardware accelerators, and continual learning.

The technologies and systems developed in this research support patients with neurological disorders or injuries of the nervous system. Current research activities are centered on artificial vision, with a particular focus on developing cell-selective closed-loop systems for next-generation retinal implants.

Contact: Dr. -Ing. Andreas Erbslöh | Recent Publication

Design of Heterogeneous AI Hardware Systems

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​​Consequently, part of our research consists of designing and implementing specialised hardware in the form of AI hardware accelerators. For this purpose, we use flexible FPGAs that allow us to implement arbitrary AI models on hardware in a cheap and efficient way. 

The hybrid hardware platform Elastic Node, which is part of the elasticAI.ecosystem, can be cons

​idered as both the fruit and instrument of our research and is designed to meet demands for usability, adaptability and monitorability, while at the same time being efficient.

For this reason, we are also investigating adequate hardware-related optimisation options for this particular area. After all, precise knowledge of the hardware allows us to find many different approaches that can be used to fully utilise the available resources. For example, there are potential savings by implementing individual model layers with quantized activation functions by means of LUTs. Other examples would be not activating certain model layers at every clock cycle, parallelisation in the ALU and many other approaches.

Contact: Dr. -Ing. Andreas Erbslöh | Recent Publication